PIC18C658T-I/L【PDF 55/246 页】IC MCU OTP 16KX16 CAN 68PLCC

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PIC18CXX8

DS30475A-page 148

Advanced Information

2000 Microchip Technology Inc.

15.4.1.1

Addressing

Once the MSSP module has been enabled, it waits for

a START condition to occur. Following the START con-

dition, the eight bits are shifted into the SSPSR register.

All incoming bits are sampled with the rising edge of the

clock (SCL) line. The value of register SSPSR<7:1> is

compared to the value of the SSPADD register. The

address is compared on the falling edge of the eighth

clock (SCL) pulse. If the addresses match, and the BF

and SSPOV bits are clear, the following events occur:

The SSPSR register value is loaded into the

SSPBUF register.

The buffer full bit BF is set.

An ACK pulse is generated.

MSSP interrupt flag bit SSPIF (PIR registers) is

set on the falling edge of the ninth SCL pulse

(interrupt is generated, if enabled).

In 10-bit address mode, two address bytes need to be

received by the slave. The five Most Significant bits

(MSb) of the first address byte specify if this is a 10-bit

address. The R/W bit (SSPSTAT register) must specify

a write so the slave device will receive the second

address byte. For a 10-bit address, the first byte would

equal ‘1111 0 A9 A8 0’, where A9 and A8 are the

two MSb’s of the address.

The sequence of events for 10-bit addressing is as fol-

lows, with steps 7- 9 for slave-transmitter:

Receive first (high) byte of address (the SSPIF,

BF and UA bits (SSPSTAT register) are set).

Update the SSPADD register with second (low)

byte of address (clears bit UA and releases the

SCL line).

Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

Receive second (low) byte of address (bits

SSPIF, BF, and UA are set).

Update the SSPADD register with the first (high)

byte of address. If match releases SCL line, this

will clear bit UA.

Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

Receive repeated START condition.

Receive first (high) byte of address (bits SSPIF

and BF are set).

Read the SSPBUF register (clears bit BF) and

clear flag bit SSPIF.

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